The present invention relates to a high-level synthesis device and a high-level synthesis method, for synthesizing a circuit in accordance with a behavioral description which describes the behavior of the circuit in a high-level language, and a recording medium on which a high-level synthesis program for synthesizing a circuit in such a manner is recorded. More specifically, the present invention relates to a high-level synthesis device and a high-level synthesis method, for synthesizing a circuit in accordance with a behavioral description including a description of synchronous communications, and a recording medium on which a high-level synthesis program for synthesizing a circuit in such a manner is recorded.
There have conventionally been some high-level synthesis methods for simulating behavior and synthesizing a circuit, in accordance with a behavioral description which describes a synchronous circuit in a language.
One of the conventional high-level synthesis methods which is employed in a behavioral synthesis system, xe2x80x9cBehavioral Compilerxe2x80x9d (a product name) manufactured by Synopsys, Inc., is as follows. Namely, the behavioral synthesis system synthesizes a register-transfer-level data of a circuit structure from a behavioral-level data of the circuit structure in accordance with an input of a behavioral description written in VHDL (VHSIC hardware description language) or Verilog-HDL (HDL: hardware description language).
In a synchronous circuit, a clock is generally used as a reference signal for determining the timing of the operation of the whole circuit. In partial circuits (such as an arithmetic unit and a register) which operate simultaneously, processing (individual processing) executed by the respective partial circuits are synchronized with each other by using the clock signal. Generally, in the steps of designing a circuit after the step of designing a register-transfer-level design (logic design), the timing of performing each operation in the circuit (at which time each operation should be executed) is determined with reference to the clock signal. It is thus possible to simulate the behavior using the clock signal as the reference signal.
However, in the step of designing a behavioral-level design (functional design) before the step of designing the register-transfer-level design, the behavior of the circuit is described without reference to the clock signal. Therefore, the timing of executing each operation is not determined until the circuit is synthesized. As a result, when the behavior of the circuit is simulated, asynchronous processes operating on different clocks may perform a data transfer without achieving synchronization with each other, thereby possibly losing the data.
For that reason, it is required to synchronize the asynchronous processes with each other. However, in the above conventional behavioral synthesis system, a command for achieving synchronization between the asynchronous processes cannot be used. Therefore, it is necessary to clearly describe, in the language, a protocol (communication procedure) for communicating data between the asynchronous processes, in order to perform the simulation by synchronizing the asynchronous processes with each other in the behavioral synthesis system.
In this case, the synchronization between the asynchronous processes is clearly described as a behavioral description on a behavioral level. Therefore, with reference to the behavioral description, the simulation in the step of designing the behavioral-level design can be carried out with the asynchronous processes synchronized with each other.
However, a circuit synthesized by the above conventional high-level synthesis method has the following problem. Namely, irrespective of whether synchronous communications between the partial circuits described by the behavioral description can be achieved without handshaking, synchronous communications between the asynchronous processes are realized by a circuit for performing the communications in accordance with the protocol, i.e., by a circuit for data communications between the asynchronous processes with handshaking.
Data communications using handshaking is performed in such a manner that data transmission and reception are carried out after confirming that preparation for transmitting and receiving data is completed. In addition, after finishing the transmission and reception of the data, it is confirmed that the data is properly transmitted and received. Therefore, in the circuit synthesized by the above high-level synthesis method, two control signal lines are always built between the partial circuits using handshaking, in addition to one data line provided for transmission and reception of data. Here, one of the two control signal lines is provided so that the sending side informs the receiving side that the data is ready to be transmitted and received, and the other is provided so that the receiving side informs the sending side that the data has been received. In this way, two control signal lines are always provided for handshaking, even when the synchronous communications between the partial circuits described by the behavioral description is realized without using handshaking. As a result, the circuit scale is enlarged, and the speed of data communications is decreased.
It is an object of the present invention to provide a high-level synthesis device and a high-level synthesis method, for synthesizing a small-scale high-speed circuit in accordance with a behavioral description which includes a description of synchronous communications and enables a simulation of the synchronous communications between asynchronous processes, and a recording medium on which a high-level synthesis program for synthesizing such a circuit is recorded.
In order to achieve the above object, a high-level synthesis device of the present invention is based on a high-level synthesis device for synthesizing a specific circuit which exhibits behavior described in a behavioral description as data indicating behavior of a circuit aimed to be synthesized, and characterized in including:
a process extraction section for extracting an available process from all processes described in a behavioral description in accordance with the behavioral description including a description of synchronous communications, the available process being a process for performing data communications through a path having no loop;
a circuit synthesis section for producing partial circuits which realize respective available processes and for connecting the partial circuits with each other, in accordance with the inputted behavioral description, so as to synthesize a specific circuit; and
a delay insertion section for inserting a delay circuit into a path that connects partial circuits with each other so that data communications between the partial circuits through a plurality of paths are synchronized with each other.
With the above structure, when inputting a behavioral description including a description (command, function, and procedure) for performing synchronous communications between asynchronous processes operating at the same time, the process extraction section of the high-level synthesis device automatically extracts an available process, which can realize the synchronous communications without handshaking, from processes included in the behavioral description. When synthesizing the circuit by connecting the partial circuits that realize the respective processes, a delay circuit is inserted into a path connecting partial circuits with each other so that the data communications between the partial circuits through a plurality of paths are synchronized with each other.
With this arrangement, in the specific circuit synthesized by the high-level synthesis device, although data communications between the available processes are performed without handshaking, partial circuits realizing the respective available processes can carry out the data communications without losing data. Therefore, even when the available processes perform the synchronous communications, a control line for handshaking can be omitted. Consequently, the specific circuit synthesized by the high-level a synthesis device has a smaller scale (area) on the whole and operates at a higher speed, compared with a circuit synthesized by the prior art requiring the control line for handshaking in order to perform the synchronous communications in the simulation on the behavioral level.
Namely, even though a behavioral description enabling the behavior of a specific circuit to be simulated, i.e., a behavioral description including a description of asynchronous processes and synchronous communications between the asynchronous processes is inputted at the stage of designing the behavioral-level design, a high-level synthesis device capable of synthesizing a small-scale high-speed specific circuit can be realized.
When determining a data communication interval of the specific circuit to be synthesized, the high-level synthesis device can employ either of the following methods. Namely, the determination of the data communication interval may be performed in accordance with the interval of the data inputted to the specific circuit or in accordance with the speed (operation speed) at which the partial circuits realizing the specific circuit operate.
When the data communication interval is determined according to the operation speed of the partial circuits, if the operation speed of the specific circuit is required to be improved, it is preferable that the high-level synthesis device has the following arrangement, in addition to the above structure. Namely, it is preferable that the high-level synthesis device further includes: (1) an interval calculation section for calculating a minimum value of a data communication interval which enables data communications with no error between the partial circuits realizing the extracted available processes; and (2) an interval determination section for determining a data communication interval of the data communications between the partial circuits, based on the minimum value, and that the circuit synthesis section synthesizes the specific circuit so that the partial circuits realizing the available processes perform the data communications at the data communication interval determined by the interval determination section.
With this arrangement, it is possible to adjust the data communication interval of the specific circuit to the practically available shortest interval under constraints of the delay time of the data transfer paths. Therefore, the operation speed of the specific circuit can be easily maximized within a realizable range.
If the specific circuit is constructed only by fastest partial circuits, the operation speed of the specific circuit will be maximized within a realizable range. However, high-speed partial circuits are generally high-power-consuming and high-cost. Therefore, if all the partial circuits are formed by the fastest partial circuits, a high-power-consuming and high-cost specific circuit will be synthesized.
On the contrary, the high-level synthesis device including the interval determination section can synthesize the specific circuit capable of operating at the same speed as the specific circuit constructed only by the fastest partial circuits, without using the fastest partial circuits for some of the partial circuits such as partial circuits except for the critical path (a path requiring the longest processing time). As a result, the high-level synthesis device capable of synthesizing a high-speed specific circuit can be supplied without much increasing the power consumed by the specific circuit and the cost of the specific circuit.
By the way, the description of the synchronous communications included in the behavioral description may be, for example, a code group indicating the protocol of the synchronous communications. In this case, however, the speed at which the high-level synthesis device synthesizes the specific circuit may be lowered because of difficulty in extracting the description of the synchronous communications from the behavioral description. In addition, if the extraction is failed, the high-level synthesis device may possibly synthesize an undesired specific circuit.
Therefore, it is preferable that the behavioral description includes, as the description of the synchronous communications, codes (for example, commands, functions, or procedures) which indicate a process including a sending operation of a data and a process including a receiving operation of the data, respectively, and that the process extraction section includes a data transfer graph generation section for recognizing the codes in the inputted behavioral description and generating a data transfer graph composed of nodes which represents respective processes and a directed edge which connects a starting node corresponding to the process including the sending operation with an end node corresponding to the process including the receiving operation.
With this arrangement, the behavioral description is, in advance, provided with specific codes as a description of the synchronous communications, and the process extraction section extracts the synchronous communications between asynchronous processes in accordance with the codes. It is thus possible to quickly and accurately generate the data transfer graph showing the data transfer between the processes. As a result, the high-level synthesis device capable of quickly and accurately synthesizing a specific circuit can be realized. In addition, since the synchronous communications between the asynchronous processes can be described by simply writing the codes, generation of the behavioral description is simplified, compared with the case where the description is generated by writing the protocol.
By the way, in order to achieve the above-mentioned object, a high-level synthesis method of the present invention is based on a high-level synthesis method for synthesizing a specific circuit which exhibits behavior described in a behavioral description as data indicating behavior of a circuit aimed to be synthesized, and characterized in including the steps of:
extracting an available process from all processes described in a behavioral description in accordance with the behavioral description including a description of synchronous communications, the available process being a process for performing data communications through a path having no loop;
synthesizing a specific circuit by producing partial circuits which realize respective available processes and by connecting the partial circuits with each other, in accordance with the inputted behavioral description; and
inserting a delay circuit into a path that connects partial circuits with each other so that data communications performed between the partial circuits through a plurality of paths are synchronized with each other. As mentioned above, the description of the synchronous communications included in the behavioral description may be, for example, a code group indicating a protocol of the synchronous communications, or specific codes (commands, functions, procedures, etc.) indicating a process including a sending operation of a data and a process including a receiving operation of the data.
With the above method, although the specific circuit is synthesized in accordance with the behavioral description enabling the simulation of the synchronous communications between asynchronous processes, control lines for handshaking can be omitted between the available processes. As a result, the above method enables the synthesis of a specific circuit which has a small scale on the whole and operates at a high speed, while allowing the simulation at a stage closer to the behavioral level.
In addition to the above-described steps, it is preferable that the high-level synthesis method further includes the steps of: (1) calculating a minimum value of a data communication interval which enables data communications with no error between the partial circuits realizing extracted available processes; and (2) determining a data communication interval of the data communications between the partial circuits, based on the minimum value, and that the step of synthesizing a specific circuit is carried out so that the partial circuits realizing available processes perform the data communications at the determined data communication interval.
With this method, it is possible to adjust the data communication interval of the specific circuit to the practically available shortest interval under constraints of the delay time of the paths through which the data is transferred. Therefore, the operation speed of the specific circuit can be easily maximized within a realizable range.
In order to achieve the above-mentioned object, a recording medium of the present invention is a recording medium storing a high-level synthesis program for synthesizing a specific circuit which exhibits behavior described in a behavioral description as data indicating behavior of a circuit aimed to be synthesized, and characterized in storing the high-level synthesis program including:
extracting an available process from all processes described in a behavioral description in accordance with the behavioral description including a description of synchronous communications, the available process being a process for performing data communications through a path having no loop;
synthesizing a specific circuit by producing partial circuits which realize respective available processes and by connecting the partial circuits with each other, in accordance with the inputted behavioral description; and
inserting a delay circuit into a path that connects partial circuits with each other so that data communications performed between the partial circuits through a plurality of paths are synchronized with each other. As mentioned above, the description of the synchronous communications included in the behavioral description is not particularly limited. The description may be, for example, a code group indicating a protocol of the synchronous communications, or specific codes (commands, functions, procedures, etc.) indicating a process including a sending operation of a data and a process including a receiving operation of the data.
When the high-level synthesis program is executed by a computer, the above-described high-level synthesis device is realized. Therefore, although the specific circuit is synthesized in accordance with the behavioral description enabling the simulation of the synchronous communications between asynchronous processes, control lines for handshaking can be omitted between the available processes. As a result, the above method enables the synthesis of a specific circuit which has a small scale on the whole and operates at a high speed, while allowing the simulation at a stage closer to the behavioral level.
Furthermore, it is preferable that the high-level synthesis program recorded on the recording medium further includes: (1) calculating a minimum value of a data communication interval which enables data communications with no error between the partial circuits realizing extracted available processes; (2) determining a data communication interval of the data communications between the partial circuits, based on the minimum value, and (3) synthesizes the specific circuit so that the partial circuits realizing the available processes perform the data communications at the determined data communication interval.
When the high-level synthesis program read out from the recording medium is executed by a computer, the above-described high-level synthesis device is realized. It is thus possible to adjust the data communication interval of the specific circuit to the practically available shortest interval under constraints of the delay time of the data transfer paths. Therefore, a high-level synthesis device enabling the operation speed of the specific circuit to be maximized within a realizable range is realized.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.